Course Calendar

INTERNATIONAL| SOLVNET

BY DESIGN PHASE


System-Level Design High-level block design, architecture design, virtual and FPGA-based prototyping, and, power electronics and wiring harness solutions		Manufacturing Mask synthesis and data prep, lithography simulation and verification and yield management

Verification High-performance system, RTL, equivalence checking, mixed-signal verification solutions, and Verification IP		TCAD Process and device simulation solutions for technology development and manufacturing

Implementation & Sign-Off Advanced digital and custom IC and FPGA design solutions, including synthesis, physical implementation, test and sign-off		Optical Design Optical design and analysis software and engineering services All Tools Directory of all Synopsys tools

REDUCE RISH WITH HIGH QUALITY IP


Interface IP Standard interfaces for SoC designs such as USB, PCIe, DDR, SATA, HDMI, MIPI and more		Logic Libraries SiWare Logic and ASAP Logic standard cell libraries for a wide array of applications and process technologies

Analog IP Analog IP such as audio codecs, data converters and video analog front-end		Processor IP ARC Processor cores, ARC Sound family, ARC Video family, configurable extensions and Sonic Focus enrichment software

Embedded Memories Embedded memory solutions including embedded SRAMs, embedded non-volatile memory and embedded test and repair		SoC Infrastructure IP minPower Components, Verification IP and the DesignWare Library including datapath IP, AMBA, foundry libraries and 8-bit microcontrollers

UNMATCHED PRODUCTIVITY FROM SYSTEM TO IMPLEMENTATION


High-Level Block Design Rapidly create and optimize differentiated IP blocks with Algorithm Design and Analysis, High-Level Synthesis, and Processor Development		Virtual Prototyping Accelerate pre-RTL embedded software development, hardware/software integration, and system validation

Architecture Design Quickly explore tradeoffs in your SoC architecture to achieve optimal product performance and cost to avoid over- or under-design		FPGA-Based Prototyping Accelerate the creation of your ASIC prototype with a high-speed hardware prototyping environment including a comprehensive software flow

Power Electronic Systems Simulate and execute behavioral design, modeling, and simulation for power electronics, multi-domain systems, and wire harnesses		System-Level Models Reduce risk and speed time to market with pre-verified models supporting industry standards for interoperability

HELPING YOUR ADDRESS YOUR TOUGHEST DESIGN CHALLANGES


Tool and Methodology Adoption Take full advantage of the latest features and methodologies available in Synopsys' tools		Design Implementation Leverage tapeout-proven flows and project experience to get your chip done

SoC Design & Verification Achieve rapid design closure by applying best practices in system-level design, RTL creation, FPGA-based prototyping, and functional verification		Low Power Optimization Implement low power implementation and verification techniques to optimize your chip's power consumption

Design Flow Deployment Optimize your design flow to address the latest design challenges		Predictable Silicon Sign-Off Improve ASIC handoff with early optimization for physical effects

SOLUTIONS FOR SEMICONDUCTOR AND SYSTEM DESIGN


End-to-End Solutions Comprehensive solutions: Eclypse Low Power Solution, System-to-Silicon (S2S) Verification Solution		Technical Platforms Integrated product platforms: Discovery Verification Platform, FPGA Design Solution, Galaxy Implementation Platform

Industry Solutions Tailored solutions for automotive, memory, mil/aero, mobile devices, & end-product categories		Lynx Design System A highly integrated, production-ready IC development platform

EXPERT TRAINING AND SUPPORT SERVICES


Training Training courses on Synopsys’ tools and methodologies		Global Support Centers Open a support issue online

SolvNet Get instant online access to the self-help support resources you need		Licensing, Installation & Compute Platforms The latest information about how to install, upgrade and manage your Synopsys licenses

EXPLORE, INTERACT AND COLLABORATE


Synopsys Users Group (SNUG) Users and product experts exchange ideas at SNUG conferences.		University Program Resources for teaching IC design: how to apply to our program, curriculum, articles, support and training, and much more

Partners Collaborating to provide advanced reference flows, design kits, libraries, IP and methodology		Interoperability EDA tools working together for customer satisfaction and success.

Blogs & Forums Insights from the experts, open forums for global community.		Conversation Central Join us the third Thursday of each month to join the conversation!

SYNOPSYS: INNOVATION AND BEYOND


About Synopsys Discover our company, our management team and our values		Synopsys Careers Learn about jobs, internships and our commitment to diversity

Press Room Read Synopsys news, contact the PR team, download an image, or gather other information		Events Meet with Synopsys at an industry event, participate at a SNUG® conference , or attend a Synopsys workshop or seminar

Investor Relations Browse information for shareholders, analysts and potential investors		Community Involvement Learn how Synopsys inspires the next generation of technologists

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Course Calendar

Location Group: North America,Virtual Classroom NA

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<< February 2012 >>

Sunday	Monday	Tuesday	Wednesday	Thursday	Friday	Saturday
			1	2	3	4
5	6	7 IC Compiler 1 [Westminster, CO] PrimeTime 1 [Austin, TX]	8 IC Compiler 1 [Westminster, CO] PrimeTime 1 [Austin, TX]	9 IC Compiler 1 [Westminster, CO] PrimeTime 1 [Austin, TX]	10	11
12	13	14 IC Compiler 1 [Mountain View, CA] SystemVerilog Testbench [NA Private]	15 IC Compiler 1 [Mountain View, CA] SystemVerilog Testbench [NA Private]	16 IC Compiler 1 [Mountain View, CA]	17 IC Compiler 2: Hierarchical Design Planning [Mountain View, CA]	18
19	20	21	22	23	24	25
26	27 DFT Compiler 1 [Mountain View, CA] SystemVerilog Testbench [Mountain View, CA]	28 DFT Compiler 1 [Mountain View, CA] SystemVerilog Testbench [Mountain View, CA]	29 DFT Compiler 1 [Mountain View, CA] SystemVerilog Testbench [Mountain View, CA]
Saturday, February 04, 2012 11:57:58 AM

<< February 2012 >>

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