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Course Catalog
Course descriptions and schedules. Please note that not all courses are available at all locations.

Advanced Synthesis with the Synplify Pro / Synplify Premier tools
The Advanced Synthesis with Synplify Pro / Premier training course enables the user to take full advantage of Synopsys’ FPGA synthesis tools. It provides in-depth information on timing-closure flow, constraints (Timing Constraints / FPGA specific constraints), integration of IP cores, hierarchical design flows, and advanced features such as TCL Find functionality.

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Assertion Based Verification (SVA)
(This class is only offered in Israel)
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Basic Training on TCAD Sentaurus Tools
This workshop will introduce users to basic concepts of how to use the following TCAD tools: SENTAURUS WORKBENCH, SENTAURUS PROCESS, ICWB, SENTAURUS STRUCTURE EDITOR, SNMESH, SENTAURUS DEVICE, TECPLOT_SV, and INSPECT. After completing the course, students should be able to set up simulations in the framework tool, starting from the mask layout and the fabrication process flow, through to the analysis of simulated DC, transient, and RF behavior of individual devices or small circuits.
Full Course Description
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Custom Designer - India
Custom Designer is an intuitive GUI based tool for capturing analog and mixed signal designs. The class consists of Foundation, Schematic Editor, and Layout Editor sections. Each section has labs that demonstrate the usage and flow of the tool. The tool and environment setup is shown in the Foundation section, while schematic entry and editing are covered in SE, and the basics of layout creation and editing are shown in LE.
Full Course Description

The price displayed is Synopsys Global List Price for training. Your actual pricing will display during check out.

This course is currently only available in India.


  		 Schedules

Design Compiler 1
This course covers the ASIC synthesis flow using Design Compiler Topographical / Graphical to generate a gate-level netlist which will result in acceptable post-placement timing and congestion. You will learn how to read, constrain, synthesize, verify logic equivalence, and analyze a complex design for timing and congestion.
Full Course Description

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  		 Schedules

Design Compiler Topographical/Graphical

This workshop covers recommended methodologies for increasing correlation and decreasing iterations between logical and physical tools by using Design Compiler Topographical/Graphical. Working from Reference Methodology seed scripts, you will explore various approaches: top-down, bottom-up, with and without floorplans, and using partial physical constraints.  Students will analyze and handle congestion and explore the primary exceptions to the core flow.  The end result will be DC-T results that correlate strongly with results from backend tools. This workshop assumes knowledge of Design Compiler using wireload models.
Full Course Description

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  		 Schedules

DFT Compiler 1
In this workshop, you will learn to use DFT Compiler to perform RTL and gate-level DFT checks and insert scan using top-down and bottom-up flows. The workshop includes an introduction to scan testing as well as advanced topics such as multi-mode scan insertion and scan compression with DFTMAX.
Full Course Description

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  		 Schedules

HSPICE Essentials
This two day workshop covers the essentials of using HSPICE: how to set up and run a simulation, including how to perform AC, DC and transient analyses. Topics include simulation algorithms, file structure, HSPICE components and syntax, viewing simulation output and more.
Full Course Description

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  		 Schedules

HSPICE Advanced Topics
This two day workshop covers using HSPICE for statistical analysis and signal integrity applications. Topics include advanced components and syntax, statistical analysis using Monte Carlo, using the field solver and, extracting S-parameters using linear analysis.
Full Course Description

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  		 Schedules

IC Compiler 1
This workshop is targeted at students who will be using IC Compiler to implement a complete physical design flow. This includes building a floorplan, performing placement, clock tree synthesis and routing, as well as chip finishing. The flows that are covered are aimed at achieving design closure for chip-level “flat” (non-hierarchical) designs with moderate timing, routeability, power, and DFT challenges. No prior standard-cell based “Automatic Place and Route” knowledge is required to attend this workshop. However, an understanding of fundamental physical design concepts is helpful.
Full Course Description

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  		 Schedules

IC Compiler 2: Clock Tree Synthesis
This advanced workshop is intended for current IC Compiler users or those who have attended the IC Compiler 1 workshop. It covers CTS problem areas including determining the correct options, performing necessary checks before starting CTS, advanced methods of controlling the synthesis process, and analyzing and debugging the results after clock trees are built.
Full Course Description

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  		 Schedules

IC Compiler 2: Hierarchical Design Planning
This course provides the foundation to use IC Compiler Design Planning effectively in performing hierarchical floorplanning using the Virtual Flat Flow. After completing the workshop the student should have all the floorplan and timing information necessary to start the Place and Route process in IC Compiler. This workshop is designed for ASIC, back-end, or layout designers with experience in the Place and Route flow using IC Compiler. It is recommended that the student attend the IC Compiler 1 workshop prior to this training.
Full Course Description

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  		 Schedules

IC Validator Beginning Users Training
In this workshop, using IC Validator – Synopsys next generation physical verication tool, you will be doing DRC/LVS checking and use VUE for debugging.

The workshop consists of three main tasks:

1) DRC module
2) LVS module
3) VUE debugging

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*This course is currently only available in India.


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Low Power Flow HLD (Front End)
In this workshop, using the Front-End Synopsys Eclypse Low Power Flow, you will synthesize and verify a multi voltage (MV) design with shutdown. The flow consists of three main tasks: 1) Specify Power intent using the IEEE P1801 Unified Power Format 2) Perform RTL synthesis and Scan insertion 3) Analyze pre-layout design Each step is MV-aware and UPF based. You will create power-intent UPF file(s). You will then take the design through RTL synthesis and scan insertion in a (hierarchical) UPF flow. Finally, you will analyze pre-layout design for MV rules, logic equivalence, timing requirements, and power consumption.
Full Course Description

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Low Power Flow P&R (Backend Flow)

This workshop teaches the design flow for back-end processing of a Multi-Voltage (MV) design using Synopsys’ Eclypse Low-Power Flow.  In the workshop you will floorplan, place, route, synthesize clocks, and verify a 65nm design with shutdown requirements. 

The course concentrates on Multi-Voltage design techniques available in IC Compiler and PrimeRail.  Power reduction techniques that are not specifically MV or those covered in basic courses are not discussed in the lectures.  Most such techniques are used in the labs and are discussed in the presentation Appendices.
Full Course Description

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  		 Schedules

PrimeTime 1
This course teaches you how to perform static timing analysis using PrimeTime. You will validate and enhance run scripts, quickly identify and debug your design violations by generating and interpreting timing reports, and remove pessimism with path-based analysis.
Full Course Description

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PrimeTime 2: Debugging Constraints

This course will teach students the "in's and out's" of understanding, investigating, tracing and identifying the pins, ports or cells involved in constraint problems encountered when performing static timing analysis using PrimeTime.
Full Course Description

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PrimeTime PX: Signoff Power Analysis
In this class, you will use PrimeTime PX to analyze time-based peak power and average power. This involves choosing the applicable method of analysis based on the activity annotation and analysis needs (vector-free and RTL vs. gate-level simulation data). These choices will influence your choice of a debugging technique, covered in this workshop. Using the UPF-based analysis flow, you will analyze multi-voltage designs and report the power consumption, as well as analyze pre-layout clock network power which includes power estimation, power annotation, and determining power savings due to clock gating. This course is typically taken after the PrimeTime1 workshop.
Full Course Description


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PrimeTime SI: Crosstalk Delay and Noise
The PrimeTime SI workshop teaches you how to increase the precision of your Static Timing Analysis (STA) with crosstalk effects. You will learn how to expand and refine your design constraints for signal integrity analysis, improving the accuracy of crosstalk calculation. At the end of the class you should be able to specify more precise relationships between your clocks and to define nets that should be included or excluded from crosstalk analysis, which slews are used for delay calculation, and timing windows for crosstalk analysis.
Full Course Description

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Saber Designer Mixed-Signal & Mixed-Technology Simulation
This three day workshop prepares students to use Saber for both design and verification work with electronic, mechatronic, mixed-signal or hydraulic systems.
Course material includes a brief overview of common Saber use methods for both design and verification processes.
In this workshop, students will become proficient creating schematics in Saber Sketch, performing a variety of different simulations and analyses using the Saber simulator, and analyzing simulation results using CosmosScope.

This workshop replaces the Saber Introductory Workshop. Students who have completed Saber Introductory should not take this class.
Full Course Description

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STAR Memory System™ Version 4.x Product Training
The STAR Memory System course is designed to help new users of the STAR Memory System (SMS) version 4.0 product develop an understanding of the system’s capabilities. Upon completion of the course, users will have a good understanding of the SMS and they will be prepared to implement a test and repair solution for embedded memories into their SoC design.
Full Course Description

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STAR Memory System™ Version 4.x Product Training (Virtual Classroom)
The STAR Memory System course is designed to help new users of the STAR Memory System (SMS) version 4.0 product develop an understanding of the system’s capabilities. Upon completion of the course, users will have a good understanding of the SMS and they will be prepared to implement a test and repair solution for embedded memories into their SoC design.

This virtual class consists of four half days of lecture. Students can run labs at their convenience by downloading them to their own compute environment. Lab Guides with answers are provided.

Full Course Description


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StarRC

In this workshop, students will learn the fundamentals of extracting RC parasitics, which are a critical component of chip-level sign-off for power, timing, and signal integrity. This course covers the different flows associated with StarRC including cell vs. transistor-level extraction, top-level vs. in-context hierarchical extraction, Milkyway vs. LEF/DEF flows, and Hercules vs. Calibre flows. Students will set up the required files, including ITF (Interconnect Technology Format) files,  to model advanced process characteristics and to perform sign-off parasitic extraction.
Full Course Description

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SystemVerilog Assertions
This course is a hands-on, practical workshop that introduces students to SystemVerilog Assertions to verify a device under test using VCS. After finishing this class students will be able to write, use, compile and debug SystemVerilog Assertions. This course is geared towards Verification and Design Engineers.
Full Course Description

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SystemVerilog Assertions - India
Assertion based verification methodology has recently become a mainstream advanced verification methodology because of its myriad advantages. Assertions help capture the designer’s intent unambiguously and concisely thereby helping the designers to communicate the assumptions and specification in an executable format. Assertions also help Verification engineers to describe higher level protocol specifications in highly concise format and are highly reusable across designs, projects etc. SystemVerilog provides rich set of constructs for building assertions. It also enables creation of pre-defined checker libraries. Another benefit of assertions is that they can be used with dynamic and formal technologies.
Full Course Description


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SystemVerilog Testbench
In this intensive, three-day course, you will learn the key features and benefits of the SystemVerilog testbench language and its use in VCS. You will learn how to develop an interface between the SystemVerilog test program and the Device Under Test (DUT), while using intuitive object-oriented technology in SystemVerilog testbench. This course concludes with an in-depth discussion of functional coverage including a uniform, measurable definition of functionality and the SystemVerilog constructs that allow you to assess the percentage of functionality covered.
Full Course Description

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SystemVerilog Testbench - India
In this intensive, three-day course, you will learn the key features and benefits of the SystemVerilog testbench language and its use in VCS. You will learn how to develop an interface between the SystemVerilog test program and the Device Under Test (DUT), while using intuitive object-oriented technology in SystemVerilog testbench. This course concludes with an in-depth discussion of functional coverage including a uniform, measurable definition of functionality and the SystemVerilog constructs that allow you to assess the percentage of functionality covered. Full Course Description


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SystemVerilog Testbench with VCS – Israel
This course teaches the key features and benefits of the SystemVerilog testbench language and its use in VCS. This course will provide the skills required to write an object-oriented SystemVerilog testbench and verify a device under test with coverage-driven random stimulus.

Concepts covered during the course include developing an interface between the SystemVerilog test program and the Device Under Test (DUT), random stimulus generation, language syntax, coding style recommendations, object oriented programming concepts, functional coverage and verification methodology (VMM) introduction.

During lab exercises the student will get practical experience in writing and debugging SystemVerilog testbench code using VCS and testbench debugger (DVE).
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SystemVerilog Verification using UVM 1.1

The EDA industry standards group, Accellera, has officially published a SystemVerilog verification methodology standard called UVM 1.1.  This standard for verifying Verilog, SystemVerilog and VHDL RTL designs is universally supported by all EDA vendors.  In this course, you will learn how to build a scalable and configurable coverage-driven UVM 1.1 SystemVerilog testbench.

Full Course Description

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SystemVerilog Verification using VMM 1.1
In this course, you will learn to apply the VMM 1.1 explicitly-phased Methodology using SystemVerilog language. It is recommended that you take the SystemVerilog Testbench workshop before this class.
Full Course Description

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SystemVerilog Verification using VMM 1.2
In this course, you will learn to apply the VMM 1.2 implicitly-phased methodology using the SystemVerilog language. It is recommended that you take the SystemVerilog Testbench workshop before this class. Full Course Description

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TetraMAX 1
In this course you will learn how to use TetraMAX to perform ATPG for stuck-at faults on a post-layout chip netlist for a scan design.
Full Course Description

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TetraMAX 2: DSMTest ATPG
In this course, you will learn how to use TetraMAX to perform ATPG for at-speed fault models for both external and internal PLL capture clocks. Topics include: ATPG for small delay defects; transition faults; and path delay faults.
Full Course Description

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