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This course covers the ASIC synthesis flow using Design Compiler. You will learn how to read, constrain, synthesize, and analyze a complex design for area and timing. You will also verify the logic equivalence of a synthesized netlist to that of an RTL design.
This course covers the ASIC synthesis flow using Design Compiler. You will learn how to read, constrain, synthesize, and analyze a complex design for area and timing. You will also verify the logic equivalence of a synthesized netlist to that of an RTL design. Full Course Description The price displayed is Synopsys Global List Price for training. Your actual pricing will display during check out.
This workshop covers recommended methodologies for increasing correlation and decreasing iterations between logical and physical tools by using Design Compiler Topographical/Graphical. Working from Reference Methodology seed scripts, you will explore various approaches: top-down, bottom-up, with and without floorplans, and using partial physical constraints. Students will analyze and handle congestion and explore the primary exceptions to the core flow. The end result will be DC-T results that correlate strongly with results from backend tools. This workshop assumes knowledge of Design Compiler using wireload models.
This workshop is targeted at students who will be using IC Compiler to implement a complete physical design flow, with a goal of achieving design closure for chip-level “flat” (non-hierarchical) designs with moderate timing, routeability, power and DFT challenges. Topics include: building a floorplan; performing placement; clock tree synthesis, and routing; and chip finishing.. No prior standard-cell based automatic place and route knowledge is required. However, an understanding of fundamental physical design concepts is helpful.
In this workshop, using the Front-End Synopsys Eclypse Low Power Flow, you will synthesize, analyze, and verify a 65nm Multi Voltage (MV) design requiring shutdown. The flow consists of four main tasks:
1) Specify Power intent using the IEEE P1801 Unified Power Format, 2) Verify design functionality and MV rules, 3) Perform power-aware RTL synthesis and Scan insertion 4) Analyze and verify pre-layout design
Each step is MV-aware and UPF based: You will start with Multi-Voltage libraries and the design description consisting of RTL, UPF, SDC, and DEF files. Using a voltage-aware simulator, you will first verify the RTL design for power intent and functionality. You will then take the design through RTL synthesis and power-domain-aware scan insertion. Next you will analyze the pre-layout design for timing requirements, power consumption, and logic equivalence. Finally, you will check for MV-rules and sign-off the design for physical implementation. Full Course Description
This workshop teaches the design flow for back-end processing of a Multi-Voltage (MV) design using Synopsys’ Eclypse Low-Power Flow. In the workshop you will floorplan, place, route, synthesize clocks, and verify a 65nm design with shutdown requirements.
The course concentrates on Multi-Voltage design techniques available in IC Compiler and PrimeRail. Power reduction techniques that are not specifically MV or those covered in basic courses are not discussed in the lectures. Most such techniques are used in the labs and are discussed in the presentation Appendices.
This course teaches you how to perform static timing analysis using PrimeTime. You will validate and enhance run scripts, quickly identify and debug your design violations by generating and interpreting timing reports, remove pessimism with path-based analysis, and generate ECO fixing guidance to downstream tools. Full Course Description
This course will teach students the "in's and out's" of understanding, investigating, tracing and identifying the pins, ports or cells involved in constraint problems encountered when performing static timing analysis using PrimeTime. Full Course Description
This workshop will show you how to use PrimeTime PX to analyze time-based peak power and average power. You will learn to:
This course is typically taken after the PrimeTime1 workshop. Full Course Description
This workshop replaces the Saber Introductory Workshop. Students who have completed Saber Introductory should not take this class. Full Course Description
In this workshop, students will learn the fundamentals of extracting RC parasitics, which are a critical component of chip-level sign-off for power, timing, and signal integrity. This course covers the different flows associated with StarRC including cell vs. transistor-level extraction, top-level vs. in-context hierarchical extraction, Milkyway vs. LEF/DEF flows, and Hercules vs. Calibre flows. Students will set up the required files, including ITF (Interconnect Technology Format) files, to model advanced process characteristics and to perform sign-off parasitic extraction.
This course prepares you to smoothly introduce the constrained randomization and coverage driven verification methodologies into your verification flow.
Coverage Driven Verification with Constrained Randomization offers advantages over traditional verification methodologies and HDL based testbenches. The IEEE standard SystemVerilog language provides a rich set of constructs and supports the efficient building the test benches to achieve high quality design verification.
This training will introduce a verification methodology that takes full advantage of SystemVerilog language features for the testbench implementation. Advanced topics including object oriented programming, randomization, threads and virtual interfaces are covered. Hands-on lab sessions provide an opportunity to implement concepts.
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