This workshop is targeted at students who will be using IC Compiler to implement a complete physical design flow, with a goal of achieving design closure for chip-level “flat” (non-hierarchical) designs with moderate timing, routeability, power and DFT challenges.  Topics include: building a floorplan; performing placement;  clock tree synthesis, and routing; and chip finishing.. No prior standard-cell based automatic place and route knowledge is required.  However, an understanding of fundamental physical design concepts is helpful.

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