In this workshop, using the Front-End Synopsys Eclypse Low Power Flow, you will synthesize, analyze, and verify a 65nm Multi Voltage (MV) design requiring shutdown.  The flow consists of four main tasks:

1)   Specify Power intent using the IEEE P1801 Unified Power Format,
2)   Verify design functionality and MV rules,
3)   Perform power-aware RTL synthesis and Scan insertion
4)   Analyze and verify pre-layout design

Each step is MV-aware and UPF based: You will start with Multi-Voltage libraries and the design description consisting of RTL, UPF, SDC, and DEF files. Using a voltage-aware simulator, you will first verify the RTL design for power intent and functionality. You will then take the design through RTL synthesis and power-domain-aware scan insertion. Next you will analyze the pre-layout design for timing requirements, power consumption, and logic equivalence. Finally, you will check for MV-rules and sign-off the design for physical implementation.
Full Course Description

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