This workshop covers recommended methodologies for increasing correlation and decreasing iterations between logical and physical tools by using Design Compiler Topographical/Graphical. Working from Reference Methodology seed scripts, you will explore various approaches: top-down, bottom-up, with and without floorplans, and using partial physical constraints.  Students will analyze and handle congestion and explore the primary exceptions to the core flow.  The end result will be DC-T results that correlate strongly with results from backend tools. This workshop assumes knowledge of Design Compiler using wireload models.

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