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algorithm design
,
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virtual platforms
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mechatronics
and
wiring harness
Manufacturing
Mask synthesis
and
data prep
,
lithography simulation
and
verification
and
yield management
Verification
High-performance system,
RTL
,
equivalence checking
, and
mixed-signal verification
solutions
TCAD
Process
and
device
simulation solutions for technology development and manufacturing
Implementation & Sign-Off
Advanced digital and
custom IC
and
FPGA
design solutions, including
synthesis
,
physical implementation
,
test
and
sign-off
All Tools
Directory of all Synopsys tools
REDUCE RISH WITH HIGH QUALITY IP
Interface and Standards IP
Broad portfolio of interface IP such as
USB
,
PCIe
,
DDR
,
SATA
,
HDMI
,
MIPI
and more
Verification IP
Portfolio of standard bus interfaces such as
USB
,
PCIe
,
SATA
and more
Analog IP
Portfolio of analog IP such as
Data Converters
,
Audio Codecs
,
Video Analog Front Ends
and more
minPower Components
Low power datapath architectures and instantiable IP extends battery life in mobile applications and reduces power consumption for SoCs
DesignWare Library
Library of design and verification IP:
Datapath
,
AMBA
,
Star IP
and more
Vertical Markets
Data Center
,
Digital Home
,
Digital Office
,
Mobile Multimedia
,
Storage
,
Wireless
HELPING YOUR ADDRESS YOUR TOUGHEST DESIGN CHALLANGES
Tool & Methodology Deployment
Take full advantage of the latest tool features and methodologies
Verfication
Accelerate adoption of advanced verification methodologies
Flow Optimization
Integrate proven flows and sub-flows to address your key design challenges
System-Level Modeling
Build transaction-level models (TLMs) and virtual platforms for pre-silicon software development
Implementation
Experts use the latest Synopsys technology, flows and infrastructure to help you get to tapeout
SOLUTIONS FOR SEMICONDUCTOR AND SYSTEM DESIGN
Eclypse Low Power Solution
The perfect alignment of technology, methodology,
IP
,
services
, and
industry standards
to address advanced low power design
Discovery Verification Platform
An integrated portfolio of
functional
,
AMS
, formal and
low-power verification
tools
Galaxy Implementation Platform
A comprehensive solution for cell-based and
custom IC implementation
Synplicity FPGA Design Solution
Comprehensive toolsets, methodologies, and services to address FPGA design requirements
Industry Solutions
Tailored solutions for
automotive
,
mobile devices
,
memory
& end-product categories
Lynx Design System
A highly integrated, production-ready IC development platform
EXPERT TRAINING AND SUPPORT SERVICES
Training
Training courses
on Synopsys’ tools and methodologies
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support issue
online
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Get instant online access to the self-help
support resources
you need
Licensing, Installation & Compute Platforms
The latest information about how to
install
, upgrade and manage your
Synopsys licenses
EXPLORE, INTERACT AND COLLABORATE
Synopsys Users Group (SNUG)
Users and product experts exchange ideas at
SNUG conferences
.
University Program
Resources for teaching IC design:
how to apply
to our program,
curriculum
,
articles
,
support and training
, and much more
Partners
Collaborating to provide advanced reference flows, design kits, libraries, IP and
methodology
Interoperability
EDA tools working together for customer satisfaction and success
Blogs & Forums
Insights from the experts, open forums for global Synopsys community
SYNOPSYS: INNOVATION AND BEYOND
About Synopsys
Discover our company, our
management team
and our
values
Synopsys Careers
Learn about
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and our
commitment to diversity
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potential investors
Community Involvement
Learn how Synopsys inspires the
next generation of technologists
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IC Compiler 2: Hierarchical Design Planning
This course provides the foundation to use IC Compiler Design Planning effectively in performing hierarchical floorplanning using the Virtual Flat Flow. After completing the workshop the student should have all the floorplan and timing information necessary to start the Place and Route process in IC Compiler. This workshop is designed for ASIC, back-end, or layout designers with experience in the Place and Route flow using IC Compiler. It is recommended that the student attend the IC Compiler 1 workshop prior to this training.
Full Course Description
If you do not see a date or location that works for you
please contact us
.
Course Type: Public
Language: English
March 5, 2010 - March 5, 2010
9:00AM - 5:00PM
Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna
Germany - Synopsys GmbH
Travel Info
Details
Price: $600.00 (USD)
Education Credits: 1
Add to Cart
Course Type: Public
Language: Hebrew
March 11, 2010 - March 11, 2010
9:00AM - 5:00PM
Local Time
Herzelia, Israel
Travel Info
Details
Price: $500.00 (USD)
Education Credits: 1
Add to Cart
Course Type: Public
March 30, 2010 - March 30, 2010
9:00AM - 5:00PM
Austin, TX
Travel Info
Details
Price: $600.00 (USD)
Education Credits: 1
Add to Cart
Course Type: Public
April 27, 2010 - April 27, 2010
9:00AM - 5:00PM
Marlboro, MA
Travel Info
Details
Price: $600.00 (USD)
Education Credits: 1
Add to Cart
Course Type: Public
May 7, 2010 - May 7, 2010
9:00AM - 5:00PM
Mountain View, CA
Travel Info
Details
Price: $600.00 (USD)
Education Credits: 1
Add to Cart
Course Type: Public
Language: English
May 21, 2010 - May 21, 2010
9:00AM - 5:00PM
Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna
Germany - Synopsys GmbH
Travel Info
Details
Price: $600.00 (USD)
Education Credits: 1
Add to Cart
Course Type: Public
Language: French
June 4, 2010 - June 4, 2010
9:00AM - 5:00PM
Central Europe Time
Grenoble, France
Travel Info
Details
Price: $600.00 (USD)
Education Credits: 1
Add to Cart
Course Type: Public
August 27, 2010 - August 27, 2010
9:00AM - 5:00PM
Mountain View, CA
Travel Info
Details
Price: $600.00 (USD)
Education Credits: 1
Add to Cart
Course Type: Public
September 28, 2010 - September 28, 2010
9:00AM - 5:00PM
Austin, TX
Travel Info
Details
Price: $600.00 (USD)
Education Credits: 1
Add to Cart
Course Type: Public
October 26, 2010 - October 26, 2010
9:00AM - 5:00PM
Marlboro, MA
Travel Info
Details
Price: $600.00 (USD)
Education Credits: 1
Add to Cart
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