IC Compiler 2: Clock Tree Synthesis
 

OVERVIEW

This advanced workshop is intended for current IC Compiler users or those who have attended the IC Compiler 1 workshop.
The workshop covers the topics users may overlook when running CTS. These topics include using the correct options and performing checks prior to starting CTS. After the clock trees are built, an in-depth knowledge is required to analyze and debug the results.

You will learn how to explore the clock tree structure using various reporting commands and the CTS GUI to analyze and verify proper settings for CTS. The workshop goes in-depth into clock tree synthesis methodology and flows for typical 90nm and 65nm designs. The users will also learn how to use the log to understand the tool messages that are critical to analyzing and debugging CTS results.

The workshop is accompanied by comprehensive hands-on labs, which provide an opportunity to apply key concepts covered during the lectures.

OBJECTIVES

At the end of this workshop the student will be able to:

• Analyze the clock tree structure prior to running CTS
• Check for valid clock definitions
• Use the clock options correctly
• Identify good vs. bad buffers/inverters for CTS
• Specify different buffers/inverters for specific optimizations within CTS
• Use Non-Default Routing rules (NDR) appropriately
• Understand and use the various IC Compiler CTS flows
• Perform clock tree synthesis in debug mode to obtain additional tool messages
• Debug QoR

AUDIENCE PROFILE

ASIC, back-end or layout designers with experience in standard cell-based automatic Place and Route using IC Compiler.

PREREQUISITES

To benefit the most from the material presented in this workshop, students should have working knowledge of Physical Design using IC Compiler.

COURSE OUTLINE

Day 1

• Pre-CTS Check and Setup
• Building Clock Trees
• Debugging and Refining Clock Trees

SYNOPSYS TOOLS USED

IC Compiler 2007.03