Overview
We start off covering how to load the required synthesis and physical data required by IC Compiler (data setup). We then show you how to create a floorplan, including power grid, which is likely to meet timing and routeability throughout the flow (design planning). The placement flow focuses on optimizing the placement and logic for timing, congestion, power and scan-chain ordering. In the CTS unit we cover controlling and building clock trees, performing additional timing optimization, followed by routing of the clock nets. In the routing unit we cover signal routing and optimization steps based on the new Zroute mode, including concurrent via doubling and antenna fixing. In the chip finishing unit we cover steps to improve yield and reliability, including wire spreading/widening, diode insertion, inserting filler cells, redundant via insertion, and metal filling.

Every lecture is accompanied by a comprehensive hands-on lab.

• Perform data setup, which includes loading required synthesis and physical data, creating a Milkyway design library, and applying common timing and optimization controls
• Create a non-hierarchical chip-level floorplan that will be routable and will achieve timing closure
• Perform placement and related optimizations to minimize timing violations, congestion, and power
• Analyze congestion maps and timing reports
• Perform pre-CTS power optimization
• Perform clock tree synthesis
• Analyze clock and timing results post-CTS
• Route the clock nets
• Execute a Zroute-based signal routing flow, with concurrent via doubling and antenna fixing
• Analyze and fix physical DRC and LVS violations
• Perform functional ECOs
• Perform chip finishing steps
• Generate output files required for final validation/verification

Audience Profile
ASIC, back-end, or layout designers who will be using IC Compiler to implement a complete physical design flow.

Prerequisites
Prior knowledge of standard-cell based automatic place & route is not needed. An understanding of fundamental physical design concepts and terms is helpful, including the following: Layout, standard cell, standard cell library, setup and hold timing, inputs and outputs of synthesis, floorplan, standard cell placement, congestion, clock tree, metal layer, via, routing. Must be able to use a text editor (vi, vim, emacs) in a UNIX environment.

• Introduction and Overview
• Data Setup and Basic Flow
• Design Planning

• Design Planning (Lab continued)
• Placement
• Clock Tree Synthesis

• Clock Tree Synthesis (Lab continued)
• Routing
• Chip Finishing
• Customer Support

• IC Compiler 2009.06