Overview
This course covers the transistor-level static timing tool NanoTime. Topics include the use of NanoTime to analyze and diagnose critical paths at block or top level of a chip. Students learn to use NanoTime to find timing violations and estimate overall performance of a design. They also learn to generate ETM models of a block for use in hierarchical analysis, either within NanoTime or with other tools such as PrimeTime.

Separate course modules are dedicated to advanced features within NanoTime such as what-if analysis, DCS/DDS (dynamic simulation of portions of the design), and multi-voltage analysis.

Labs are available to allow the student to acquire first-hand experience with NanoTime.

• Use basic NanoTime commands
• Know where commands are used in a NanoTime flow
• Use NanoTime to analyze and diagnose critical paths on a design
• Use NanoTime to create an ETM model
• Use NanoTime in a hierarchical flow

Audience Profile
Design, verification, or CAD engineers who understand transistor-level designs and want to verify timing on digital CMOS blocks.

Prerequisites
Experience in the following areas is recommended to gain the most value from the workshop content:

• Transistor level analysis
• Basic knowledge of static timing

• Introduction
• NanoTime Usage Methodology (Lab)
• NanoTime Detailed Phases
• NanoTime versus PrimeTime

• Introduction
• Save & Restore (Lab)
• Active Miller Effect (Lab)
• DCS/DDS (Lab)
• Multi-Voltage Analysis (Lab)
• Multi-Operating Conditions (Lab)
• Modification of Timing Checks (Lab)
• What-if Analysis (Lab)
• Custom Reporting (Lab)
• Hierarchical SoC Flow
• Transparent ETM (Lab)
• Characterize Context (Lab)
• Merge Model (Lab)
• Logic Constraints
• Simultaneous Switching
• Topology Database (Lab)

• NanoTime 2008.12 release or later version