NanoTime and NanoTime Ultra: Transistor Level Static Timing Analysis
blueline  

OVERVIEW

This course covers the transistor-level static timing tools: NanoTime and NanoTime Ultra. Topics include the use of NanoTime to analyze and diagnose critical paths at block or top level of a chip. Students learn to use NanoTime to find timing violations and estimate overall performance of a design. They also learn to generate ETM and CCS models of a block for use in hierarchical analysis, either within NanoTime or with other tools such as PrimeTime. Finally, they learn to use SI-delay analysis and PBSA (path based slack analysis) on the design along with other features in NanoTime Ultra.

Separate course modules are dedicated to advanced features within NanoTime such as what-if analysis, DCS/DDS (dynamic simulation of portions of the design), and multi-voltage analysis.  Another module is available to learn to migrate a design analyzed in PathMill to a NanoTime analysis, using NanoTime migration scripts to convert the run commands and then to compare the results.

Labs are available in many modules to allow the student to acquire first-hand experience with NanoTime and NanoTime Ultra.


OBJECTIVES
After completing this workshop, the student should be able to:

  • Use basic NanoTime commands
  • Know where commands are used in a NanoTime flow
  • Use NanoTime to analyze and diagnose critical paths on a design
  • Use NanoTime to create an ETM model
  • Use NanoTime in a hierarchical flow
  • Use NanoTime Ultra to analyze a design with PBSA and SI analysis
  • Use NanoTime Ultra to generate CCS timing model

AUDIENCE PROFILE

Design, verification, or CAD engineers who understand transistor-level designs and want to verify timing on digital CMOS blocks.

PREREQUISITES

Experience in the following areas is recommended to gain the most value from the workshop content:

  • Transistor level analysis
  • Basic knowledge of static timing

COURSE OUTLINE

Basic NanoTime

  • NanoTime Usage Methodology (Lab)
  • NanoTime Detailed Phases
  • NanoTime versus PrimeTime
NanoTime Migration
  • Migration Flow
  • Migration Methodology (Lab)
  • NT versus PM
  • Migration Script Details


Advanced Features

  • Save & Restore
  • Active Miller Effect
  • DCS/DDS
  • Multi-Voltage Analysis
  • Multi-Operating Conditions (Lab)
  • Modification of Timing Checks
  • What-if Analysis
  • Custom Reporting
  • Hierarchical SoC Flow
  • Transparent ETM (Lab)
  • Characterize Context
  • Merge Model
  • Logic Constraints
  • Simultaneous Switching
  • Topology Database


NanoTime Ultra

  • PBSA (Lab)
  • SI-Delay (Lab)
  • SOI (Lab)
  • Virtual Ground (Lab)
  • CCS Timing Module Suport

SYNOPSYS TOOLS USED

  • NanoTime 2007.12  release or later version

 blueline