NanoTime: Transistor Level Static
Timing Analysis
OVERVIEW
This course covers the transistor-level static timing tool NanoTime. Topics included in this course include the use of NanoTime to analyze and diagnose critical paths at block or top level of a chip. Students will learn how to use NanoTime to find timing violations and estimate overall performance of a design. They will also learn how to generate ETM models of a block for use in hierarchical analysis, either within NanoTime or with other tools such as PrimeTime.
Separate course modules are dedicated to advanced features within NanoTime such as what-if analysis, DCS/DDS (dynamic simulation of portions of the design), multi-voltage analysis, migrating a design analyzed in PathMill to a NanoTime analysis, using NanoTime migration scripts to convert the run commands and then to compare the results.
Labs help the student to acquire first hand experience with NanoTime. .
OBJECTIVES
After completing this workshop, the student will be able to:
- Use basic NanoTime commands
- Know where commands are used in a NanoTime flow
- Use NanoTime to analyze and diagnose critical paths on a design
- Use NanoTime to create an ETM model
- Use NanoTime in a hierarchical flow
- Use the migration scripts to convert a PathMill run into a NanoTime run and compare the results.
AUDIENCE PROFILE
Design, verification or CAD engineers who understand transistor-level designs and want to verify timing on digital CMOS blocks.
PREREQUISITES
Experience in the following areas is recommended to gain the most value from the workshop content:
- Transistor level analysis
- Basic knowledge of static timing
COURSE OUTLINE
Day 1
Basic Nanotime
- Introduction
- NanoTime Usage Methodology (Lab)
- NanoTime Detailed Phases
- Netlist
- Clocks
- Topology Recognition
- Timing Checks
- Topology Reporting
- Timing Assertions
- Handling Parasitics
- Timing Exceptions
- Analysis Setup
- Path Reporting
- Multi-Analysis
- NanoTime versus PrimeTime
NanoTime Migration
- Introduction
- Migration Flow
- Migration Methodology (Lab)
- NT versus PM
- Migration Script Details
Day 2
Advanced Features
- Introduction
- Save & Restore
- Active Miller Effect
- DCS/DDS
- Multi-Voltage Analysis
- Multi-Operating Conditions (Lab)
- Modification of Timing Checks
- What-if Analysis
- Custom Reporting
- Hierarchical SoC Flow
- Transparent ETM (Lab)
- Characterize Context
- Merge Model
- Logic Constraints
- Simultaneous Switching
- Topology Database
SYNOPSYS TOOLS USED
- NanoTime 2007.06 release or later version