Overview
This course covers the transistor-level static timing tool: NanoTime Ultra. Students learn to use SI-delay analysis and PBSA (path based slack adjustment) analysis on the design along with other features in NanoTime Ultra.

Labs are available in many modules to allow the student to acquire first-hand experience with NanoTime Ultra.

• To analyze a design with PBSA and SI analysis
• To generate and read CCS timing model
• For simultaneous switching analysis for conservative min/max delay calculation

Audience Profile
Design, verification, or CAD engineers who understand transistor-level designs and want to verify timing on digital CMOS blocks.

Prerequisites
Experience in the following areas is recommended to gain the most value from the workshop content:

• NanoTime: Transistor-Level Static Timing Analysis

• Introduction
• PBSA (Lab)
• SI-Delay (Lab)
• SI-Noise (Lab)
• Simultaneous Switching (Lab)
• CCS Timing Model Support (Lab)
• SOI (Lab)
• Miscellaneous (Lab)

• NanoTime 2008.12 release or later version