Overview
This course covers the transistor-level static timing tool: NanoTime Ultra. Students learn to use SI-delay, SI-noise analyses and PBSA (path-based slack adjustment) analysis on the design along with other features in NanoTime Ultra.

Supporting labs allow the student to acquire first-hand experience with NanoTime Ultra.

• Analyze a design with PBSA and SI analysis
• Generate and read CCS timing model
• Perform simultaneous switching analysis for conservative min/max delay calculation

Audience Profile
Design, verification, or CAD engineers who understand transistor-level designs and want to verify timing on digital CMOS blocks.

Prerequisites
Experience in the following areas is recommended to gain the most value from the workshop content:

• NanoTime: Transistor-Level Static Timing Analysis

• Introduction
• PBSA (Lab)
• SI-Delay (Lab)
• SI-Noise (Lab)
• Multiple Input Switching (Lab)
• CCS Timing Model Support (Lab)
• SOI (Lab)
• Miscellaneous (Lab)

• NanoTime 2008.12 release or later version