Overview
This course introduces the uses of Power Compiler and RTL Power Estimator. You will learn to link Power PLI tasks with the VCS simulator, perform pre-synthesis power estimates using several techniques, and perform both RTL and gate-level power analysis and optimization.

• Define the test protocol for a design and customize the initialization
• Link the Power PLI using VCS
• Generate switching activity files from simulation
• Generate power estimates in RTL Power Estimator and identify power-hungry design blocks
• Use clock gating and operand isolation techniques in Power Compiler to reduce power consumption
• Generate and examine power reports in Power Compiler
• Use gate-level power optimization for further power reduction

Audience Profile
Design engineers who want an introduction to power estimation, analysis, and optimization with Power Compiler and RTL Power Estimator.

Prerequisites
To benefit the most from the material presented in this workshop, students should:

• Understand Verilog and/or VHDL
• Be able to use a Verilog or VHDL simulator
• Be familiar with UNIX workstations running X-windows
• Be familiar with Design Compiler
• Be familiar with vi, emacs, or another UNIX text editor

• Power libraries
• RTL power estimation
• RTL switching activity
• RTL Optimization (Clock Gating and Operand Isolation)

• RTL Optimization (cont)
• Gate level power analysis and optimization
• Leakage Power and Dual Vt

• Power Compiler release 2002.05-SP1
• VCS Version 6.2

• DFT Compiler 2007.03
• Design Vision 2007.03
• Design Compiler 2007.03
• TetraMAX 2007.03