Overview
This course takes you from the introduction of fundamental concepts to advanced features of PrimeRail for Full-Chip Power Grid Reliability Analysis that includes gate and transistor levels. The objective of this workshop is to provide the user the ability to use PrimeRail to perform power/ground sign-off interconnect reliability analysis for full-chip design.

As technology feature sizes shrink, conductors get smaller, and supply voltages reduce, the corresponding current per scaled feature size increases exponentially. These changes cause power-rail dynamic voltage drop and electromigration (EM) effects that significantly degrade performance and can cause the circuit to malfunction. To prevent such problems, PrimeRail provides an accurate and design-stage comprehensive sign-off solution for power consumption, Voltage drop and EM analysis for advanced-technology designs. PrimeRail is an important component of Synopsys’ Milkyway-based Galaxy solution.

With Full-Chip Reliability Analysis being a key component of today’s designs, this workshop will provide the design or verification engineer the steps required to perform static and dynamic power grid analysis. Also the course will instill the knowledge behind those steps in order to meet the reliability needs of today’s designs.

• Set up and perform Power/Ground (PG) reliability analysis for checking Static and Dynamic Voltage Drop and Electromigration (EM) potential violations
• Explanation of and/or set up the phases of Dynamic analysis of PrimeRail that involve the following:
• Library Characterization
• Data preparation
• Power Analysis
• PG Parasitic (RC) Extraction
• Dynamic (Transient) Rail Analysis
• Violation Viewing, Reporting and Correction
• What-if Analysis – Package parasitics and Decap insertion
• Voltage Drop Derated Timing Analysis
• Accurate Hard Macro Modeling
• Power Management( power switch) Cell handling
• Set up PG analysis for hierarchical and top-level
• Use the PrimeRail graphical user interface (GUI) for the PG rail analysis, including what-if analysis

Audience Profile
Design, verification or CAD engineers who perform power/ground interconnect reliability analysis at the “Block” or “Full-Chip” levels. This covers a wide spectrum of designs of digital, memory, and analog/mixed signal.

Prerequisites
Experience in the following areas is recommended to gain the most value from the workshop content:

• Physical layout
• Physical extraction
• Power simulation

• Introduction to Rail Analysis - requirements, capabilities and database preparation
• Power and Timing Model creation
• Power supply, net switching and Transition Time inputs
• Power and Rail Analysis
• Mapping, reporting, querying and what-if Analysis
• Integrated Flows - Hardmacro modeling, Power gating and Voltage derated timing analysis

• Introduction, database requirements and flows
• Library Characterization and LSF
• Cell-Level Dynamic Analysis-PP Run
• Cell-Level Dynamic Analysis-Transient Analysis
• What-if Analysis – Package Parasitics and Decap Insertion
• Mapping, waveform viewing, reporting and querying
• Tx-Level Dynamic Analysis-Data Preparation
• Tx-Level Dynamic Analysis
• Tx-Level Signal EM Analysis
• Macro Modeling - Memory, Analog, custom or Hardmacro blocks

• Primerail