SystemVerilog Testbench - India

OVERVIEW

This course prepares you to smoothly introduce the constrained randomization and coverage driven verification methodologies into your verification flow.

Coverage Driven Verification with Constrained Randomization offers advantages over traditional verification methodologies and HDL based testbenches. The IEEE standard SystemVerilog language provides a rich set of constructs and supports the efficient building the test benches to achieve high quality design verification.

This training will introduce a verification methodology that takes full advantage of SystemVerilog language features for the testbench implementation. Advanced topics including object oriented programming, randomization, threads and virtual interfaces are covered. Hands-on lab sessions provide an opportunity to implement concepts.

OBJECTIVES

At the end of this workshop the student should understand:

• Create constrained random stimulus
• Implement functional coverage models
• Implement the complete verification environment using OOP
• Connect your DUV with SystemVerilog  testbench through interfaces
• Use the DVE debugger 

AUDIENCE PROFILE

• Design / Verification Engineers

PREREQUISITES

To benefit the most from the material presented in this workshop, you should have:

• Familiarity with design verification.
• Basic programming skills in Verilog, VHDL or C
• Debugging experience with Verilog, VHDL or C

COURSE OUTLINE

• Introduction to verification methodologies
• Testbench environment
• Language Basics
• Object Oriented Programming [OOP] basics
• Randomization
• Controlling Threads
• Virtual Interfaces
• Functional Coverage
• Testbench Methodology

SYNOPSYS TOOLS USED

•  VCS 2006.06