VMM Applications - India

OVERVIEW

This course prepares you to smoothly introduce the constrained randomization and coverage driven verification methodologies into your verification flow.

Coverage Driven Verification with Constrained Randomization offers advantages over traditional verification methodologies and HDL based testbenches. The IEEE standard SystemVerilog language provides a rich set of constructs and supports the efficient building the test benches to achieve high quality design verification.

This training will introduce a verification methodology that takes full advantage of SystemVerilog language features for the testbench implementation. Advanced topics including object oriented programming, randomization, threads and virtual interfaces are covered. Hands-on lab sessions provide an opportunity to implement concepts.

OBJECTIVES

By end of course you should be able to:

  • Describe the VMM applications shipped with VCS
  • Identify the VMM Applications and functionality that would be most useful in a specific domain
  • Start leveraging the various VMM applications to ramp up the testbench environment development time and increase verification productivity

AUDIENCE PROFILE

  • Design / Verification Engineers

PREREQUISITES

  • Familiarity with design/verification flows.
  • Knowledge of SystemVerilog and VMM

COURSE OUTLINE

  • Introduction  to  VMM applications
  • VMM Register Abstraction Layer    
    • Manage  register and memory verification through RAL base classes
    • Automate Model creation, shadow DUT registers and connect to testbench
    • Leverage built in tests and coverage model to reach verification goal
  • VMM Environment Composition   
    • Create  reusable verification subsystems
    • VMM Consensus class for scalable end of test detection mechanism
    • VMM Memory Allocation Manager  for shadowing hardware memory
  •  VMM Data Stream Scoreboard
    • Pre-built self checking base classes for different types of data streams
    •  Extend base classes for user functionality and testbench integration
  •  Hardware Abstraction Layer
    • Guidelines for synthesizable VMM based BFMs
    • VMM testbenches  to target simulation or hardware assisted verification
    • Leverage transaction passing features across hardware software domains for best simulation performance.

SYNOPSYS TOOLS USED

  • VCS 2006.06