Training

Catalog

Descriptions and schedules.

Blast Boot Camp

The Blast 2005.03 "Boot Camp" IC Design course using Magma technology is an in depth class which teaches students how to manage top level or block-level physical hierarchical designs and covers all phases of technology development and design analysis and optimization. This 10 day course is taught by experts in the various aspects of using Magma to build complex flat and hierarchical designs. The course is composed of approximately 50% lecture and 50% lab work. This is an advanced course. Completion of the 3-day Blast Fusion course is highly recommended. Familiarity with the tool is required.
Full Description

Recommended Prerequisites:
Knowledge of Magma Basics required.

Agenda

There are no current schedules listed for this course, to request this course, click here.

Blast Create

Blast Create^TM is an RTL-to-placed-gates design environment that provides RTL synthesis, DFT rule checking, concurrent timing analysis, and physical synthesis. During the two-day Blast Create workshop, you are introduced to key concepts behind the Magma® FixedTiming® methodology, including a technique for synthesis without wire load models, as well as the common data model used throughout the flow. The workshop emphasizes elearning by doing with hands-on labs where you optimize a sample RTL design and generate a placement. You learn to effectively maximize the quality of your design by following the recommended front-end design flow conventional RTL synthesis topics (such as HDL support, timing constraints, and area-versus-delay tradeoffs), DFT rule checking, automatic repair, and scan insertion. During the physical synthesis training modules, you learn to make crucial architecture selections, and sizing and optimization decisions.

Agenda

There are no current schedules listed for this course, to request this course, click here.

Blast Fusion

Blast Fusion® is a complete netlist-to-GDSII chip implementation system providing optimization, place and route capabilities, useful skew clock generation, floorplanning, power planning, RC extraction, and built-in incremental timing analysis. During the three-day Blast Fusion workshop, you learn key concepts behind the Magma® FixedTiming® methodology, including a technique for synthesis without wire load models, as well as the common data model used throughout the flow. The workshop emphasizes “learning by doing” with hands-on labs where you optimize a sample design for timing and area that includes power, clock, and signal routing. You learn to effectively maximize the quality of your design by following the recommended back-end design flow—library preparation, importing and optimizing the netlist, floorplanning, power planning, and clock tree synthesis.

Agenda

There are no current schedules listed for this course, to request this course, click here.

Blast Noise

Blast Noise is part of a uniquely integrated system that works with Blast Fusion throughout the entire chip implementation phase to analyze, avoid, and adjust signal integrity violations for a correct by construction design. Blast Noise training discusses signal integrity issues, including crosstalk noise and crosstalk delay; and chip reliability issues, such as signal electromigration and wire self heat. You will discover how these problems are automatically managed in the Magma integrated system and get hands-on experience using the tool to analyze and repair designs. After running analyses and viewing reports for crosstalk noise, crosstalk delay, and signal electromigration, you will direct Blast Noise to automatically avoid and repair problems using noise-aware buffer insertion, gate sizing, track reordering and wire spacing. You will also learn the latest techniques for addressing signal integrity violations in DSM designs, including signal net and clock shielding.

Recommended Prerequisites:
Knowledge of Blast Fusion required.

Agenda

There are no current schedules listed for this course, to request this course, click here.

Blast Plan Pro

Magma's Prototyping capability enables the designer to discover design issues such as RTL or a netlist which cannot meet timing goals with its current architecture/structure, bad or missing SDC constraints, or high congestion and utilization in a fraction of the time required for a full implementation. In addition, it automates the process of creating optimal partitions for designs that will be implemented hierarchically. In this workshop, you will begin with initial constraint and timing sanity checks. You will then use massive virtually flat placement to visualize and determine optimal partitioning for the design. Next you will assign pin locations using both automatic and manual techniques and then abstract the partitions into glassbox models for hierarchical prototyping and implementation. Next you will validate your prototype in terms of timing, congestion, utilization, etc. and then prepare the partitions for final implementation by pushing down time budgeted constraints and top level power structures and blockages. The lecture is then followed by a hands-on lab; about half of the class time will be spent for lecture and half spent doing hands-on labs.

Recommended Prerequisites:
Knowledge of Magma Basics is suggested.

Agenda

There are no current schedules listed for this course, to request this course, click here.

Blast Rail

Blast Rail is part of a uniquely integrated system that works with Blast Fusion to maintain power integrity in the design. You will learn about voltage-drop analysis, voltage drop-induced delay analysis, and electromigration analysis on rail wires and vias. Hands-on analysis will provide you with familiarity with rail extraction, power and voltage drop analysis, and rail em analysis and allow you to view graphical and text reports on the results. The 'what-if' analysis training allows you to gain experience in the optimization of power integrity to reduce over-design of the power grid in today's DSM designs.

Recommended Prerequisites:
Knowledge of Blast Fusion required.

Agenda

There are no current schedules listed for this course, to request this course, click here.

FineSim

FineSim^TM SPICE is a SPICE-level simulation analysis tool that incorporates transistor-level simulation analysis capabilities for mixed signal and analog designs. This training covers different algorithms and simulation control options. Finesim engine supports distributed processing and training will cover how to run FineSim on multiple cpus on the same machine, on a network and on LSF/Sun grids. FineSim Pro (Superset of spice and fast spice) can simulate very big circuits ( fullchip simulation) and very fast simulations. This training covers Finesim Pro examples and techniques to address co-simulation ( verilog + spice) training.

Agenda

Schedules

Hydra Flow Training

Hydra flow enables Hierarchical Floorplanning with limited Automation and High flexibility of design style and is most useful for large, hierarchical designs. This will be a detailed 1 day training that will give an overview on the floorplanning and hierarchical planning flow using Hydra. Training will cover theory as well as lab exercises.

Recommended Prerequisites:
Knowledge of Magma Basics is required for this course.

Agenda

There are no current schedules listed for this course, to request this course, click here.

Quartz DRC (WebEx)

Quartz DRC is a linearly scalable sign-off design rule checker (DRC) architected to meet the through-put and accuracy requirements of nanometer designs. Quartz DRC uses an open Tcl-based procedural runset language amenable to both restricted and recommended design rules. This class gives the user the information and hands-on experience to successfully process a design using Quartz DRC, and visualize the results using a layout editor. Furthermore, it will cover the theory of distribution and offer real life examples of understanding the output that the tool generates.

Agenda

There are no current schedules listed for this course, to request this course, click here.

QuickCap NX

QuickCap is Magma's high accuracy parasitic extractor which translates a 2D layout and a technology file into a QuickCap input deck, and performs the parasitic extraction. The class starts with a brief introduction to QuickCap and then goes into the details of how to create a technology file, do resistance extraction and netlist generation with gds2cap. This is then followed by a detailed explanation on the Monte-Carlo techniques for capacitance extraction in QuickCap. You will go through the labs for self and coupling capacitance extraction. Understand the statistical behavior of QuickCap; other auxiliary programs associated with QuickCap, gds2xxx, as well as different extraction flows with labs and examples.

Agenda

There are no current schedules listed for this course, to request this course, click here.

RioMagic

RioMagic is a chip-package co-design tool. The RioMagic training class focuses on RioMagic's flip-chip design methodology and its functionalities. The class is targeted at chip designers with knowledge of floor planning and P&R. Users will learn how to import the chip and package technology and design information into the tool, how to create a prototype package-chip design from design specification and explore package choices and die sizes, how to build high quality bump templates, and most importantly, how to plan flip chip bumps, place I/O cells and complete RDL routing to assure chip and package routability, satisfy I/O and core power requirement, and resolve conflicts between chip and package constraints.

Agenda

There are no current schedules listed for this course, to request this course, click here.

SiliconSmart

SiliconSmart is Magma's standard cell and IO characterization solution used to generate timing, power, ccs, ecsm, SI (noise) and low power libraries. The SiliconSmart training class focuses on tool usage and assumes the user has a basic understanding of characterization methodology. Users will learn the command sequence used for generating libraries along with configuration options and settings for customizing libraries. The user will also learn how to define cell functionality within the tool including combinatorial, sequential and complex cells along with basic IO configurations. Liberty styling options and the liberty model API will also be covered. Common degugging scenarios will also be covered. The course has 4 labs to help students apply what has been discussed in the training course.

Agenda

Schedules

Static Timing Analysis

Magma uses a single static timing analyzer throughout the RTL-to-GDS2 design flow. This powerful incremental static timing analyzer provides high capacity, streamlines constraint generation and provides accurate timing information at every stage of the design flow. Clocks, timing constraints on input and output signals, false (impossible) paths, multi-cycle paths, and time borrowing are among the many topics that will be covered. You will learn how to specify the information that impacts STA in Blast Fusion and how to create and interpret timing reports. About one-third of class time will be spent doing hands-on labs.

Agenda

There are no current schedules listed for this course, to request this course, click here.

Talus Design

Talus® Design is an RTL-to-placed-gates design environment that provides RTL synthesis, DFT rule checking, concurrent timing analysis, and physical synthesis. During the two-day Talus Design workshop, you are introduced to key concepts behind the Magma® synthesis and design methodology, including a technique for synthesis without wire load models, as well as the common data model used throughout the flow. The workshop emphasizes learning by doing with hands-on labs where you optimize a sample RTL design and generate a placement. You learn to effectively maximize the quality of your design by following the recommended front-end design flow conventional RTL synthesis topics (such as HDL support, timing constraints, and area-versus-delay tradeoffs), DFT rule checking, automatic repair, and scan insertion. During the physical synthesis training modules, you learn to make crucial architecture selections, and sizing and optimization decisions.

Agenda

Schedules

Talus Plan Pro

Magma's Prototyping capability enables the designer to discover design issues such as RTL or a netlist which cannot meet timing goals with its current architecture/structure, bad or missing SDC constraints, or high congestion and utilization in a fraction of the time required for a full implementation. In addition, it automates the process of creating optimal partitions for designs that will be implemented hierarchically. In this workshop, you will begin with initial constraint and timing sanity checks. You will then use massive virtually flat placement to visualize and determine optimal partitioning for the design. Next you will assign pin locations using both automatic and manual techniques and then abstract the partitions into glassbox models for hierarchical prototyping and implementation. Next you will validate your prototype in terms of timing, congestion, utilization, etc. and then prepare the partitions for final implementation by pushing down time budgeted constraints and top level power structures and blockages. The lecture is then followed by a hands-on lab; about half of the class time will be spent for lecture and half spent doing hands-on labs.

Recommended Prerequisites:
Knowledge of Magma Basics suggested.

Agenda

There are no current schedules listed for this course, to request this course, click here.

Talus Vortex

Talus® Vortex is a complete netlist-to-GDSII chip implementation system providing optimization, place and route capabilities, useful skew clock generation, floorplanning, power planning, RC extraction, and built-in incremental timing analysis. During the three-day workshop, you learn key concepts behind the Magma® synthesis and design methodology, including a technique for synthesis without wire load models, as well as the common data model used throughout the flow. You learn to effectively maximize the quality of your design by following the recommended back-end design flow library preparation, importing and optimizing the netlist, floorplanning, power planning, clock tree synthesis, signal integrity driven routing, and design verification.

Agenda

Schedules

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