Course Catalog

HELPING YOU DESIGN THE CHIP INSIDE

DESIGN IMPLEMENTATION

VERIFICATION

INTELLECTUAL PROPERTY

DFM/TCAD

DESIGN SERVICES

Customer Education Services

NORTH AMERICA

Search

Calendar

Contact

Education Packages

EUROPE & ISRAEL

Search

Calendar

Contact

INDIA

Search

Calendar

Contact

ASIA PACIFIC

China

Korea

Taiwan

Singapore

Japan

FULL CATALOG

COURSE OPTIONS

TERMS & CONDITIONS

TRAINING CENTERS

DOWNLOAD LABS

�

Training Locations	My Training Profile	Credit Status

Course Catalog

Course descriptions and schedules. Please note that not all courses are available at all locations.

Assertion Based Verification (SVA)

(This class is only offered in Israel)

Schedules

Basic Training on TCAD Sentaurus Tools

This workshop will introduce users to basic concepts of how to use the following TCAD tools: SENTAURUS WORKBENCH, LIGAMENT, SENTAURUS PROCESS, SENTAURUS STRUCTURE EDITOR, MESH, SENTAURUS DEVICE, TECPLOT_SV, and INSPECT. After completing the course, students should be able to set up simulations in the framework tool, starting from the mask layout and the fabrication process flow, through to the analysis of simulated DC, transient, and RF behavior of individual devices or small circuits.
Full Course Description

Schedules

Design Compiler 1

This course covers the ASIC synthesis flow using Design Compiler. You will learn how to read, constrain and synthesize a complex design for area and timing. You will learn how to analyze the synthesis results and generate output data for downstream layout tools. The course is targeted at ASIC digital designers with little to no Design Compiler experience.
Full Course Description

Schedules

Design Compiler 1 - India

Schedules

DFT Compiler 1

In this workshop you will learn to use DFT Compiler to perform RTL and gate-level DFT checks and insert scan using top-down and bottom-up flows. This course has no prerequisites, but ideally would be taken after the Design Compiler 1 workshop. After this class, you may wish to continue your education with the TetraMAX� 1 workshop.
Full Course Description

Schedules

DFT Compiler 1 - India

Schedules

Hercules - India

This workshop provides basic training on Hercules verification and usage and basic training on writing DRC and LVS runsets. The class includes hands on labs to reinforce what is learned in the lectures.
Full Course Description

The price displayed is Synopsys Global List Price for training.� Your actual pricing will display during check out.

Schedules

HSIMplus - India

This two-day basic training will teach you how to use the Synopsys HSIM FastSpice simulator. It will introduce HSIMplus, a comprehensive platform for simulation and analysis of high performance analog, mixed-signal, memory, and system on-chip designs including important post-layout effects. You will learn the basic HSIM technology, timing and power analysis and the way to fine tune the parameters to get the desired accuracy or speed. The class includes hands-on labs to enhance your understanding of concepts taught in the class, including HSIM command line execution, interactive commands to debug the circuits, methods to setup the back-annotation simulation, and the HSIM-VCS Co-Simulation.
Full Course Description

The price displayed is Synopsys Global List Price for training. Your actual pricing will display during check out.

Schedules

HSPICE Essentials

This two day workshop covers the essentials of using HSPICE: how to set up and run a simulation, including how to perform AC, DC and transient analyses. Topics include simulation algorithms, file structure, HSPICE components and syntax, viewing simulation output and more.
Full Course Description

Schedules

HSPICE Essentials - India

Schedules

HSPICE Advanced Topics

This two day workshop covers using HSPICE for statistical analysis and signal integrity applications. Topics include advanced components and syntax, statistical analysis using Monte Carlo, using the field solver and, extracting S-parameters using linear analysis.
Full Course Description

Schedules

IC Compiler - India

At the end of this workshop, you will be able to use IC Compiler to perform placement, power, DFT, CTS, routing, SI and optimizations, achieving design closure for moderate to high challenge designs. You will also learn how to perform Design for Manufacturing tasks, as well as produce a flat floorplan (automatic macro placement) using IC Compiler's Design Planning features. You will learn how to optimize the design using multiple constraints and operating conditions using the new Multi Scenario capability. This course is primarily targeted at students with a working knowledge of Physical Compiler or Astro, or other Place and Route tools.
Full Course Description

The price displayed is Synopsys Global List Price for training.� Your actual pricing will display during check out.

Schedules

IC Compiler 1

Schedules

IC Compiler 2: Clock Tree Synthesis

At the end of this workshop, you will be able to use IC Compiler to perform pre-CTS checks and build clock trees to achieve good QoR. The workshop will discuss how to perform debugging and identifying problem areas that can prevent ICC-CTS from achieving better QoR. This is an advanced workshop primarily targeted at students with a working knowledge of IC Compiler or who have attended the IC Compiler 1 workshop.
Full Course Description

Schedules

IC Compiler 2: Hierarchical Design Planning

This course provides the foundation to use IC Compiler Design Planning effectively in performing hierarchical floorplanning using the Virtual Flat Flow. After completing the workshop the student should have all the floorplan and timing information necessary to start the Place and Route process in IC Compiler. This workshop is designed for ASIC, back-end, or layout designers with experience in the Place and Route flow using IC Compiler. It is recommended that the student attend the IC Compiler 1 workshop prior to this training.
Full Course Description

Schedules

Introductory TCAD Training

This course will focus on the basic usage of TCAD tools for simulating fabrication processes and electrical behavior of devices. You will learn how to set up simulation of fabrication flows starting from the mask layout, through the analysis of simulated DC, transient, and RF behavior of individual devices or small circuits, inspect results in the visualization tool and organize/manage projects in the workbench tool.
Full Course Description

Schedules

MAST Modeling

The MAST Modeling course will give the student the ability to use Saber more effectively by: explaining how to parameterize existing models, how to develop macro models, how to develop simple device models, and how to develop an understanding of general device models.
Full Course Description

Schedules

Nanosim

The course teaches you the basics of the NanoSim engine, and how to set up and run a simulation. NanoSim is a superset of TimeMill and PowerMill, and includes all features available in those two tools.
Full Course Description

Schedules

Nanosim Advanced

This workshop teaches you the advanced features of NanoSim and goes into greater depth on a number of topics discussed in basic NanoSim training. Topics covered include: simulation algorithms and modes; interactive debug; timing checks; power analysis; Nanosim-VCS Co-simulation; and Post-layout simulation.

The workshop will also describe the basic concepts behind the NanoSim simulator and how they impact simulator performance and accuracy.
Full Course Description

Schedules

NanoTime and NanoTime Ultra: Transistor Level Static Timing Analysis

This course takes you from the introduction of fundamental concepts through advanced features of NanoTime and NanoTime Ultra for transistor-level static timing, including the usage of scripts to convert PathMill runs to NanoTime. The objective of this workshop is to provide the user the ability to use NanoTime and NanoTime Ultra to perform static timing analysis on large blocks, create .lib models for use in hierarchical analysis, and run signal integrity delay analysis.
Full Course Description

Schedules

Nanotime: Transistor Level Static Timing Analysis

This course takes you from the introduction of fundamental concepts through advanced features of NanoTime for transistor-level static timing, including the usage of scripts to convert PathMill runs to NanoTime. This workshop will help the user master the use of NanoTime to perform static timing analysis on large blocks, create .lib models for use in hierarchical analysis.
Full Course Description

Schedules

OpenVera Reference Verification Methodology (RVM)

In this intensive, two-day hands-on course, you will learn to effectively use the Verification Methodology Manual (VMM) based RVM classes in both VERA and VCS ntb environments. You will learn how to use these RVM classes to build a testbench environment to implement any test with minimal or no modification. This course requires OpenVera knowledge, and is typically taken after the Vera 1 workshop.
Full Course Description

Schedules

PrimeTime 1

This workshop will enable you to perform static timing analysis using PrimeTime. You will learn how to quickly and effectively identify and debug your design violations by generating and interpreting timing reports. You will master the skills required to investigate and gain familiarity with the clocks that will largely dictate your STA results. At the end of the workshop, you will know how to use a straightforward and simple methodology to create and execute error-free run scripts.
Full Course Description

Schedules

PrimeTime 1 - India

Schedules

PrimeTime 2: Debugging and Constraining Custom Clocks

Constraining custom clock logic for Static Timing Analysis can be a difficult, but common and necessary, task. In Static Timing Analysis, you are often handed designs containing custom clock logic. By default, this custom clock logic produces different results in a static analysis tool such as PrimeTime than it does in a dynamic tool such as a logic simulator. This course teaches you how STA chooses waveform edges, and how to constrain PrimeTime so that it gives you the desired result. You will also learn how to identify and handle clock problems.
Full Course Description

Schedules

PrimeTime 2: Debugging Constraints

This course will teach students the "in's and out's" of understanding, investigating, tracing and identifying the pins, ports or cells involved in constraint problems encountered when performing static timing analysis using PrimeTime.
Full Course Description

Schedules

PrimeTime PX: Signoff Power Analysis

This class will help you learn to use PrimeTime PX to analyze Peak Power and Average Power by determining what power analysis method is applicable based on the given data and analysis needs (vector-free and RTL vs. Gate-level simulation data). You will analyze multi-voltage designs and report the power consumption using both the UPF and non-UPF-based flows. You will also estimate pre-layout clock tree power. Finally, you will determine the quality of annotation data and the analysis performed in order to choose an appropriate debugging technique. This course is typically taken after the PrimeTime1 workshop.
Full Course Description

Schedules

PrimeTime SI: Crosstalk Delay and Noise

Schedules

PrimeTime SI: Crosstalk Delay and Noise - India

The PrimeTime SI course teaches you how to increase the precision of your STA with crosstalk effects. It also teaches you how to further increase the accuracy of your STA by defining more exact design-specific crosstalk-affecting relationships between paths, by focusing on important elements of your analysis, and by implementing key advanced-timing functionality. Classroom PrimeTime SI training is delivered in one full day; Virtual Classes are delivered in two half-day sessions.
Full Course Description��

The price displayed is Synopsys Global List Price for training.� Your actual pricing will display during check out.

Schedules

Saber Designer Mixed-Signal & Mixed-Technology Simulation

This three day workshop prepares students to use Saber for both design and verification work with electronic, mechatronic, mixed-signal or hydraulic systems.
Course material includes a brief overview of common Saber use methods for both design and verification processes.
In this workshop, students will become proficient creating schematics in Saber Sketch, performing a variety of different simulations and analyses using the Saber simulator, and analyzing simulation results using CosmosScope.

This workshop replaces the Saber Introductory Workshop. Students who have completed Saber Introductory should not take this class.
Full Course Description

Schedules

Saber Designer Mixed-Signal & Mixed-Technology Simulation - Michigan

This two day workshop prepares students to use Saber for both design and verification work with electronic, mechatronic, mixed-signal or hydraulic systems.
Course material includes a brief overview of common Saber use methods for both design and verification processes. In this workshop, students will become proficient creating schematics in Saber Sketch, performing a variety of different simulations and analyses using the Saber simulator, and analyzing simulation results using CosmosScope.

Schedules

Star-RCXT

Timing and Signal Integrity analysis for the Chip-level sign-off requires the annotation of accurate RC parasitics. In this workshop, students will learn the fundamentals of RC Extraction. This course also covers the different flows associated with Star-RCXT including; cell vs. transistor-level extraction, top-level vs. in-context hierarchical extraction, Milkyway vs. LEF/DEF flow, and Hercules vs. Calibre flows. Students will also set up the required files, like ITF (Interconnect Technology Format) to model advanced process characteristics (example: 90 nm), and perform sign-off parasitic extraction
Full Course Description

Schedules

Star-RCXT - India

Schedules

System Verilog Assertion - India

Assertion based verification methodology has recently become a mainstream advanced verification methodology because of its myriad advantages. Assertions help capture the designer�s intent unambiguously and concisely thereby helping the designers to communicate the assumptions and specification in an executable format. Assertions also help Verification engineers to describe higher level protocol specifications in highly concise format and are highly reusable across designs, projects etc. SystemVerilog provides rich set of constructs for building assertions. It also enables creation of pre-defined checker libraries. Another benefit of assertions is that they can be used with dynamic and formal technologies.
Full Course Description

The price displayed is Synopsys Global List Price for training.� Your actual pricing will display during check out.

Schedules

SystemVerilog Testbench

In this intensive, three-day course, you will learn the key features and benefits of the SystemVerilog testbench language and its use in VCS. You will learn how to develop an interface between the SystemVerilog test program and the Device Under Test (DUT), while using intuitive object-oriented technology in SystemVerilog testbench. This course concludes with an in-depth discussion of functional coverage including a uniform, measurable definition of functionality and the SystemVerilog constructs that allow you to assess the percentage of functionality covered.
Full Course Description

Schedules

SystemVerilog Testbench - India

This course prepares you to smoothly introduce the constrained randomization and coverage driven verification methodologies into your verification flow.

Coverage Driven Verification with Constrained Randomization offers advantages over traditional verification methodologies and HDL based testbenches. The IEEE standard SystemVerilog language provides a rich set of constructs and supports the efficient building the test benches to achieve high quality design verification.

This training will introduce a verification methodology that takes full advantage of SystemVerilog language features for the testbench implementation. Advanced topics including object oriented programming, randomization, threads and virtual interfaces are covered. Hands-on lab sessions provide an opportunity to implement concepts.

Full Course Description

The price displayed is Synopsys Global List Price for training. Your actual pricing will display during check out.

Schedules

SystemVerilog Testbench with VCS

This course teaches the key features and benefits of the SystemVerilog testbench language and its use in VCS. This course will provide the skills required to write an object-oriented SystemVerilog testbench and verify a device under test with coverage-driven random stimulus.

Concepts covered during the course include developing an interface between the SystemVerilog test program and the Device Under Test (DUT), random stimulus generation, language syntax, coding style recommendations, object oriented programming concepts, functional coverage and verification methodology (VMM) introduction.

During lab exercises the student will get practical experience in writing and debugging SystemVerilog testbench code using VCS and testbench debugger (DVE).

Schedules

SystemVerilog Verification Using VMM Methodology

In this intensive, two-day hands-on course, you will learn to apply the VMM Methodology (based on the Verification Methodology Manual � VMM) effectively in SystemVerilog testbenches. You will learn how to use VMM base classes to build a SystemVerilog test environment that can implement any test with minimal or no modification. This course requires SystemVerilog testbench knowledge, and is typically taken after the SystemVerilog Testbench workshop.
Full Course Description

Schedules

SystemVerilog Verification Using VMM Methodology - India

Schedules

TetraMAX 1

Schedules

TetraMAX 1 - India

In this workshop you will learn how to use TetraMAX to perform ATPG for stuck-at faults on a post-layout chip netlist for a scan design. This course is typically taken after the DFT Compiler 1 workshop.
Full Course Description

The price displayed is Synopsys Global List Price for training.� Your actual pricing will display during check out.

Schedules

TetraMAX 2: DSM Testing

This class will show you how to use TetraMAX to perform ATPG, targeting different fault models. This workshop details the Transition Fault Model, enabling you to quickly edit your existing stuck-at SPF files and scripts to use them for Transition ATPG. You will learn about the Timing exceptions and the various flows to merge your Stuck-At and Transition patterns. This course is typically taken after the TetraMAX 1 workshop.
Full Course Description

Schedules

VERA I

This course is a hands-on workshop that re-enforces the verification concepts taught in lecture through a series of intense labs. At the end of this class, students should have the skills required to write an object-oriented OpenVera testbench to verify a device under test with coverage-driven random stimulus using VCS and Vera.
Full Course Description

Schedules

VMM Applications--India

VMM Applications provide a collection of high-level functions and methodology guidelines to reduce testbench creation time for commonly used design elements, including registers, memories and self-checking structures to enable easier reuse of testbench components.
This training presents the different applications packages that are shipped with VCS, maps their usage in various contexts of verification environments and showshow to apply them to increase verification productivity. Hands-on lab sessions provide an opportunity to adopt these applications easily and efficiently in your own testbenches. Full Course Description

The price displayed is Synopsys Global List Price for training. Your actual pricing will display during check out.

Schedules

Back

ViewCentral Privacy Statement
Copyright � 2008 Rainmaker Systems, Inc. All rights reserved.